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CAT5269
Dual Digitally Programmable Potentiometers (DPPTM) with 256 Taps and 2-wire Interface
FEATURES
Four linear taper digitally programmable potentiometers 256 resistor taps per potentiometer End to end resistance 50 k or 100 k Potentiometer control and memory access via 2-wire interface (I2C like) Low wiper resistance, typically 100 Nonvolatile memory storage for up to four wiper settings for each potentiometer Automatic recall of saved wiper settings at power up 2.5 to 6.0 volt operation Standby current less than 1 A 1,000,000 nonvolatile WRITE cycles 100 year nonvolatile memory data retention 24-lead SOIC and TSSOP packages Industrial temperature range For Ordering Information details, see page 15.
DESCRIPTION
The CAT5269 is two digitally programmable poten- tiometers (DPPsTM) integrated with control logic and 18 bytes of NVRAM memory. Each DPP consists of a series of resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 8-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 8-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a 2-wire serial bus. On power-up, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control registers. The CAT5269 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. It is available in the -40C to 85C industrial operating temperature ranges and offered in a 24-lead SOIC and TSSOP package.
FUNCTIONAL DIAGRAM PIN CONFIGURATION
SOIC (W) TSSOP (Y)
NC A0 NC NC NC NC VCC RLO RHO 1 2 3 4 5 6 7 8 9 24 A3 23 SCL 22 NC 21 NC 20 NC 19 NC 18 GND 17 RW1 16 RH1 15 RL1 14 A1 13 SDA
WP A0 A1 A2 A3 CONTROL LOGIC NONVOLATILE DATA REGISTERS RL0 RL1 RW1 SCL SDA 2-WIRE BUS INTERFACE WIPER CONTROL REGISTERS RH0 RH1
RW0
RWO 10 A2 11 12 WP
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Doc. No. MD-2123 Rev. F
CAT5269 PIN DESCRIPTIONS
SCL: Serial Clock The CAT5269 serial clock input pin is used to clock all data transfers into or out of the device. SDA: Serial Data The CAT5269 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with the other open drain or open collector I/Os. A0, A1, A2, A3: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of sixteen devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5269. RH, RL: Resistor End Points The two sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The RW pins are equivalent to the wiper terminal of a mechanical potentiometer. : Write Protect Input WP The pin when tied low prevents nonWP volatile writes to the data register (change of wiper control register is allowed) and when tied high or left floating normal read/write operations are allowed. See Write Protection on page 7 for more details.
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name NC A0 NC NC NC NC VCC RL0 RH0 RW0 A2 WP SDA A1 RL1 RH1 RW1 GND NC NC NC NC SCL A3 Function No Connect Device Address, LSB No Connect No Connect No Connect No Connect Supply Voltage Low Reference Terminal for Potentiometer 0 High Reference Terminal for Potentiometer 0 Wiper Terminal for Potentiometer 0 Device Address Write Protection Serial Data Input/Output Device Address Low Reference Terminal for Potentiometer 1 High Reference Terminal for Potentiometer 1 Wiper Terminal for Potentiometer 1 Ground No Connect No Connect No Connect No Connect Bus Serial Clock Device Address
DEVICE OPERATION
The CAT5269 is two resistor arrays integrated with a 2-wire serial interface, two 8-bit wiper control registers and eight 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode.
Doc. No. MD-2123 Rev. F
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CAT5269
ABSOLUTE MAXIMUM RATINGS(1) Parameters Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to VSS(1) (2) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25C) Lead Soldering Temperature (10 s) Wiper Current RECOMMENDED OPERATING CONDITIONS Parameters VCC Industrial Temperature POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol RPOT RPOT Parameter Potentiometer Resistance (100 k) Potentiometer Resistance (50 k) Potentiometer Resistance Tolerance RPOT Matching Power Rating Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Resolution Absolute Linearity (5) Relative Linearity (6) Temperature Coefficient of RPOT Ratiometric Temp. Coefficient Potentiometer Capacitances Frequency Response Test Conditions Min Limits Typ. 100 50 Max Units k k 20 25C, each pot IW = 3 mA @ VCC = 3 V IW = 3 mA @ VCC = 5 V VSS = 0 V Rw(n)(actual)-R(n)(expected)(8) Rw(n+1)-[Rw(n)+LSB](8) (4) (4) (4) RPOT = 50 k (4) 300 20 10/10/25 0.4 200 100 VSS 0.4 1 0.2 1 50 3 300 150 VCC % % mW mA V % LSB (7) LSB (7) ppm/C ppm/C pF MHz Ratings +2.5 to +6 -40 to +85 Units V C Ratings -55 to +125 -65 to +150 -2.0 to +VCC + 2.0 -2.0 to +7.0 1.0 300 6 Units C C V V W C mA
IW RW RW VTERM
TCRPOT TCRATIO CH/CL/CW fc
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. (3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1 V to VCC +1 V. (4) This parameter is tested initially and after a design or process change that affects the parameter. (5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (7) LSB = RTOT / 255 or (RH - RL) / 255, single pot (8) n = 0, 1, 2, ..., 255
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Doc. No. MD-2123 Rev. F
CAT5269
D.C. OPERATING CHARACTERISTICS VCC = +2.5 V to +6.0 V, unless otherwise specified. Symbol ICC1 ICC2 ISB ILI ILO VIL VIH VOL1 Parameter Power Supply Current Power Supply Current Non-volatile WRITE Standby Current (VCC = 5 V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3 V) IOL = 3 mA Test Conditions fSCL = 400 kHz, SDA = Open VCC = 6 V, Inputs = GND fSCK = 400 kHz, SDA Open VCC = 6 V, Input = GND VIN = GND or VCC, SDA = Open VIN = GND to VCC VOUT = GND to VCC -1 VCC x 0.7 Min Max 1 5 5 10 10 VCC x 0.3 VCC + 1.0 0.4 Units mA mA A A A V V V
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5 V Symbol CI/O(1) CIN
(1)
Test Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, A3, SCL, ) WP
Conditions VI/O = 0 V VIN = 0 V
Max 8 6
Units pF pF
A.C. CHARACTERISTICS 2.5V - 6.0V Symbol fSCL TI
(1)
Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SLC Low to SDA Data Out and ACK Out Time the bus must be free before a new transmission can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
Min
Max 400 200 1
Units kHz ns s s s s s s ns ns
tAA tBUF
(1)
1.2 0.6 1.2 0.6 0.6 0 50 0.3 300 0.6 100
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF
(1) (1)
s ns s ns
tSU:STO tDH
Note:
This parameter is tested initially and after a design or process change that affects the parameter.
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(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT5269
POWER UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms
WIPER TIMING Symbol tWRPO tWRL Parameter Wiper Response Time After Power Supply Stable Wiper Response Time After Instruction Issued Max 10 10 Units s s
WRITE CYCLE LIMITS (3) Symbol tWR Parameter Write Cycle Time Max 5 Units ms
RELIABILITY CHARACTERISTICS Symbol NEND
(1)
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
Min 1,000,000 100 2000 100
Max
Units Cycles/Byte Years V mA
TDR(1) VZAP(1) ILTH(1)
Notes: (1) (2) (3)
This parameter is tested initially and after a design or process change that affects the parameter. tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Figure 1. Bus Timing
tF tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR
SDA IN tAA SDA OUT tDH tBUF
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Doc. No. MD-2123 Rev. F
CAT5269 SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5269 will be considered a slave device in all applications. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5269 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT5269 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5269 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.
Write Operations
In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of CAT5269. The instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the selected register. The CAT5269 acknowledges once more and the Master generates the STOP condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT5269 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5269 is still busy with the write operation, no ACK will be returned. If the CAT5269 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 0101 for the CAT5269 (see Figure 5). The next four significant bits (A3, A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to sixteen devices may be individually addressed by the system. Typically, +5V and ground are hard-wired to these pins to establish the device's address. After the Master sends a START condition and the slave address byte, the CAT5269 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT5269 responds with an acknowledge after receiving a START condition and its slave address. If
Doc. No. MD-2123 Rev. F
Write Protection
The Write Protection feature allows the user to protect against inadvertent programming of the non-volatile data registers. If the pin is tied to LOW, the data WP registers are protected and become read only. Similarly, the pin going low after start will interrupt WP a nonvolatile write to data registers, while the pin WP going low after an internal write cycle has stated will have no effect on any write operation (see also CAT5409 or CAT5259). The CAT5269 will accept both slave addresses and instructions, but the data registers are protected from programming by the device's failure to send an acknowledge after data is received.
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(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT5269
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT BYTE n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 3. Start/Stop Condition
SDA
SCL START CONDITION STOP CONDITION
Figure 4. Acknowledge Condition
SCL FROM MASTER 1 8 9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 5. Slave Address Bits CAT5269 0 1 0 1 A3 A2 A1 A0
* **
A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device. A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
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Doc. No. MD-2123 Rev. F
CAT5269 INSTRUCTION AND REGISTER DESCRIPTION
SLAVE ADDRESS BYTE The first byte sent to the CAT5269 from the master/processor is called the Slave/DPP Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5269 are fixed at 0101[B] (refer to Table 1). The next four bits, A3 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 - A0 input pins for the CAT5269 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 Figure 6. Write Timing
BUS ACTIVITY: MASTER SDA LINE S T A R T
S
inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE The next byte sent to the CAT5269 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I3 - I0. The R1 and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of four Wiper Control Registers. The format is shown in Table 2. Data Register Selection Data Register Selected DR0 DR1 R1 0 0 R0 0 1
SLAVE/DPP ADDRESS
Fixed Variable
INSTRUCTION BYTE
op code
Register Pot1 WCR Address Address
DR1 WCRDATA
S T O P P
A C K
A C K
A C K
Table 1. Identification Byte Format
Device Type Identifier Slave Address
ID3 0 (MSB)
ID2 1
ID1 0
ID0 1
A3
A2
A1
A0 (LSB)
Table 2. Instruction Byte Format
Instruction Opcode Data Register Selection WCR/Pot Selection
I3 (MSB)
I2
I1
I0
R1
R0
P1
P0 (LSB)
Doc. No. MD-2123 Rev. F
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CAT5269
WIPER CONTROL AND DATA REGISTERS Wiper Control Register (WCR) The CAT5269 contains two 8-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. The Wiper Control Register is a volatile register that loses its contents when the CAT5269 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers (DR) Each potentiometer has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the Table 3. Instruction Set Instruction Read Wiper Control Register Write Wiper Control Register Read Data Register Write Data Register XFR Data Register to Wiper Control Register XFR Wiper Control Register to Data Register Gang XFR Data Registers to Wiper Control Registers Gang XFR Wiper Control Registers to Data Register Increment/Decrement Wiper Control Register
Note: 1/0 = data is one or zero
four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 10 ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data. INSTRUCTIONS Four of the nine instructions are three bytes in length. These instructions are: -- Read Wiper Control Register - read the current wiper position of the selected potentiometer in the WCR -- Write Wiper Control Register - change current wiper position in the WCR of the selected potentiometer -- Read Data Register - read the contents of the selected Data Register -- Write Data Register - write a new value to the selected Data Register The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions
I3 1 1 1 1 1
I2 0 0 0 1 1
I1 0 1 1 0 0
I0 1 0 1 0 1
Instruction Set R1 R0 WCR1/P1 0 0 1/0 0 1/0 1/0 1/0 0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
WCR0/P0 1/0 1/0 1/0 1/0 1/0
Operation
Read the contents of the Wiper Control Register pointed to by P1-P0 Write new value to the Wiper Control Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and R1R0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Data Register pointed to by P1-P0 and R1R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P1-P0 to the Data Register pointed to by R1R0 Transfer the contents of the Data Registers pointed to by R1-R0 of both pots to their respective Wiper Control Registers Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of both pots Enable Increment/decrement of the Control Latch pointed to by P1-P0
1
1
1
0
1/0
1/0
1/0
1/0
0
0
0
1
1/0
1/0
0
0
1
0
0
0
1/0
1/0
0
0
0
0
1
0
0
0
1/0
1/0
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Doc. No. MD-2123 Rev. F
CAT5269
exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWR. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or the transfer can occur between both potentiometers and one associated register. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5269; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: -- XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. -- XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. Figure 7. Two-Byte Instruction Sequence
SDA 0 1 0 1 A2 A1 A0 Internal Address A I3 C K I2 I1 I0 R1 R0 P1 P0 Register Address A C K Pot/WCR Address S T O P
-- Gang XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. -- Gang XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 9 and 10). The Increment/Decrement command is different from the other commands. Once the command is issued and the CAT5269 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instructions format for more detail.
S ID3 ID2 ID1 ID0 A3 T A R Device ID T
Instruction Opcode
Figure 8. Three-Byte Instruction Sequence
SDA 0 1 0 1 A2 A0 A I3 C K Internal Address A1 I2 I1 I0 R1 R0 P1 P0 A C K Data Pot/WCR Register Address Address D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] A C K S T O P
S ID3 ID2 ID1 ID0 A3 T A Device ID R T
Instruction Opcode
Figure 9. Increment/Decrement Instruction Sequence
SDA S T A R T
0
1
0
1 A3 A2 A1 A0 Internal Address A C K I3 I2 I1 I0 A C Pot/WCR K Data Address Register Address R1 R0 P1 P0 I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P
ID3 ID2 ID1 ID0 Device ID
Instruction Opcode
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(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT5269
Figure 10. Increment/Decrement Timing Limits
INC/DEC Command Issued SCL
tWRL
SDA
RW
Voltage Out
INSTRUCTION FORMAT
Read Wiper Control Register (WCR) INSTRUCTION DATA S DEVICE ADDRESSES A A AS T0101AAAAC100100PPC76543210 C T A KO 3210K 10K R P T Write Wiper Control Register (WCR) S DEVICE ADDRESSES A INSTRUCTION DATA A AS T0101AAAAC101000PPC76543210 C T A KO 3210K 10K R P T Read Data Register (DR) S DEVICE ADDRESSES A INSTRUCTION DATA A AS T0101AAAAC1011RRPPC76543210 C T A KO 3210K 1010K R P T Write Data Register (DR) S DEVICE ADDRESSES A INSTRUCTION DATA A AS T0101AAAAC1100RRPPC76543210 C T A KO 3210K 1010K R P T
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Doc. No. MD-2123 Rev. F
CAT5269 INSTRUCTION FORMAT (continued)
Gang Transfer Data Register (DR) to Wiper Control Register (WCR) INSTRUCTION S DEVICE ADDRESSES A AS T0101AAAAC0001RR00CT A KO 3210K 10 R P T Gang Transfer Wiper Control Register (WCR) to Data Register (DR) S DEVICE ADDRESSES A INSTRUCTION AS T0101AAAAC1000RR00CT A KO 3210K 10 R P T Transfer Wiper Control Register (WCR) to Data Register (DR) S DEVICE ADDRESSES A INSTRUCTION AS T0101AAAAC1110RRPPCT A 3210K 1010KO R P T Transfer Data Register (DR) to Wiper Control Register (WCR) S DEVICE ADDRESSES A INSTRUCTION AS T0101AAAAC1101RRPPCT A 3210K 1010KO R P T Increment (I)/Decrement (D) Wiper Control Register (WCR) S DEVICE ADDRESSES A INSTRUCTION A T0101AAAAC001000PPC I I A 3210K 10K/ / R DD T DATA ... S IIT / /O DDP
Note: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Doc. No. MD-2123 Rev. F
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CAT5269 PACKAGE OUTLINE DRAWINGS
SOIC 24-LEAD 300 mils (W)
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1 E
2.35 0.10 2.05 0.31 0.20 15.20 10.11 7.34 1.27 BSC 0.25 0.40 0 5
2.65 0.30 2.55 0.51 0.33 15.40 10.51 7.60 0.75 1.27 8 15
c D E E1 e h
b PIN#1 IDENTIFICATION
e
L 1
TOP VIEW
D
h
h
1
A
A2
1 END VIEW
A1 SIDE VIEW
L
c
Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-013.
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Doc. No. MD-2123 Rev. F
CAT5269
TSSOP 24-LEAD 4.4 mm (Y)
b
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1 E
1.20 0.05 0.80 0.19 0.09 7.70 6.25 4.30 7.80 6.40 4.40 0.65 BSC 1.00 REF 0.50 0 0.60 0.70 8 0.15 1.05 0.30 0.20 7.90 6.55 4.50
c D E E1 e L L1 1
e TOP VIEW
D c A2 A 1 L1 L SIDE VIEW END VIEW
A1
Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-153.
Doc. No. MD-2123 Rev. F
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CAT5269 EXAMPLE OF ORDERING INFORMATION
Prefix CAT Device # 5269 Suffix W
Package W: SOIC Y: TSSOP
(1)
I
Temperature Range I = Industrial (-40C to 85C)
-00
Resistance 50: 50 k 00: 100 k
- T1
Tape & Reel T: Tape & Reel 1: 1000/Reel - SOIC 2: 2000/Reel - TSSOP
Company ID Product Number 5269
ORDERING INFORMATION
Orderable Part Number CAT5269WI-50-T1 CAT5269WI-00-T1 CAT5269YI-50-T2 CAT5269YI-00-T2 CAT5269WI50 CAT5269WI00 CAT5269YI50 CAT5269YI00 Resistance (k) 50 100 50 100 50 100 50 100 Package SOIC TSSOP Matte-Tin SOIC TSSOP Lead Finish
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) This device used in the above example is a CAT5269WI-00-T1 (SOIC, Industrial Temperature, 100 k, Tape & Reel).
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15
Doc. No. MD-2123 Rev. F
CAT5269 REVISION HISTORY
Date 18-Nov-03 06-May-04 Revision A B Description Initial Issue Added TSSOP package in all areas Updated Functional Diagram Updated Pin Descriptions Updated notes in Absolute Max Ratings Updated Potentiometer Characteristics table Updated DC Characteristics table Added Wiper Timing table Updated Write Cycle Limits table Changed Figure 3 drawing to Start/Stop Condition from Start/Stop Timing Changed Figure 4 title to Acknowledge Condition (from Acknowledge Timing) Updated Table 3 Gang XFR Operation information Corrected Instruction Format for Gang Transfer Data Register (DR) to Wiper Control Register (WCR) Updated Example of Ordering Information Update Package Outline Drawings Added MD- to document number Update Potentiometer Characteristics table Update D.C. Operating Characteristics table Update Wiper Timing table Change logo and fine print to ON Semiconductor Update Ordering Information table
16-Oct-07 17-Oct-08 25-Nov-08 31-Jul-09
C D E F
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PUBLICATION ORDERING INFORMATION
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Doc. No. MD-2123 Rev. F
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(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice

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